Huawei Ascend AI Chips: Specs, Models, and 2027 Roadmap Explained

China’s leading AI labs are increasingly training frontier models on Huawei Ascend processors — homegrown AI chips that directly rival NVIDIA’s data-center GPUs. The z ai platform and other frontier labs now run their entire training stack on Ascend hardware, following US export restrictions that cut off access to A100 and H100 chips. This guide covers every Ascend generation from the 910 series to the upcoming 970, real-world performance numbers, and how the Atlas SuperCluster is reshaping global AI infrastructure.

The Ascend lineup spans from the production-proven 910B to the planned 960 and 970 generations, with system-level products like the Atlas 950 SuperPoD dwarfing NVIDIA’s NVL144 by 56.8x in scale and 15x in total memory.

What Are Huawei Ascend AI Chips?

HiSilicon — Huawei’s in-house semiconductor design arm — develops the Ascend processors for large-scale AI training and inference workloads. The chips are engineered to replace NVIDIA GPUs across Chinese data centers, an urgent priority after US export restrictions cut off access to A100 and H100 hardware. Huawei’s Ascend lineup competes directly with NVIDIA’s data-center portfolio and enables China’s AI industry to operate independently of US-controlled compute.

The Ascend series was not born as a reaction to sanctions alone. HiSilicon had been designing AI accelerators since 2018, and the Ascend 910 debuted before the first major export controls took effect. What changed after 2022 — and especially after January 2025 — was urgency: every major Chinese AI lab formalized an Ascend-first strategy, and Huawei’s production volumes scaled accordingly.

Design and Purpose

Ascend chips are purpose-built for matrix-heavy AI workloads: large language model training, image generation, and inference at data-center scale. Unlike general-purpose GPUs, the Ascend architecture prioritizes tensor operations and data movement efficiency. The chips pair with Huawei’s MindSpore framework and the Atlas server line, forming a vertically integrated stack from silicon to software — a deliberate parallel to NVIDIA’s CUDA/GPU ecosystem. Huawei maintains the official Ascend developer portal with full SDK and hardware documentation.

The Ascend ecosystem consists of four integrated layers:

• Silicon: Ascend chips designed by HiSilicon, fabricated at SMIC
• Memory and interconnect: HiZQ 2.0 HBM and UnifiedBus 2.0 / HiBL 1.0
• Servers: Atlas 800T A2 and Atlas 900 series rack units
• Software: MindSpore framework with CUDA compatibility layer via SIMT

The Strategic Context

After the US Entity List additions of January 2025, Chinese AI labs — including Zhipu AI, DeepSeek, and Baidu — turned to Ascend chips as their primary compute substrate. Huawei projected $12 billion in AI chip revenue for 2026, up from $7.5 billion in 2025, as NVIDIA’s China market share approached zero. The scale of this shift is without precedent in semiconductor history: an entire national AI industry pivoting to a single domestic supplier within 18 months.

Huawei Ascend Chip Generations: Full Model Lineup

The Ascend chip family spans three production generations and two on-roadmap generations, each with distinct performance targets and manufacturing characteristics.

Ascend 910 Series (Current Production)

The Ascend 910B is Huawei’s workhorse chip. GLM-5 — Zhipu AI’s 744-billion-parameter frontier model — was trained on a cluster of 100,000 Ascend 910B chips, which remains the most documented large-scale Ascend deployment to date. The improved Ascend 910c uses a 7nm SMIC node with DUV lithography, delivering 800 TFLOP/s at FP16 and 3.2 TB/s memory bandwidth.

The manufacturing constraint is significant: 7nm DUV yields run at approximately 30%, meaning roughly two-thirds of fabricated dies are discarded. Despite this, Huawei shipped approximately 600,000 Ascend 910C units in 2026, with total Ascend die production across all models projected up to 1.6 million for the year. Volume compensates for yield.

Ascend 950 and 950PR (2026 Flagship)

The Ascend 950 reaches 1 PFLOPS at FP8 and 2 PFLOPS at MXFP4 — marking a generational jump from the 910 series. The 950PR variant goes further: it outperforms the NVIDIA H20 by 2.87x on compute throughput and is the only Chinese AI chip to support FP4 precision inference — a capability reserved for NVIDIA’s H100 NVL and later in the global market.

The Ascend 950DT doubles the memory density to 144 GB of HiZQ 2.0 HBM — Huawei’s proprietary high-bandwidth memory — with 4 TB/s bandwidth and 2 TB/s chip-to-chip interconnect via UnifiedBus 2.0. The DT variant targets the largest training runs, where memory capacity is as critical as compute throughput.

Ascend 960 and 970 (Roadmap)

The Ascend 960 is planned for Q4 2027, targeting approximately double the compute of the 950 generation. The 970 follows in Q4 2028. Huawei’s rotating chairman Eric Xu announced the 3-year roadmap publicly, signaling a disciplined cadence toward ZFLOP-scale compute — without relying on TSMC EUV lithography. The Atlas 960 SuperCluster derived from the 960 chip is projected to deliver 2 ZFLOPS at FP8 and 4 ZFLOPS at FP4, putting it on par with or ahead of NVIDIA’s next-generation data-center roadmap.

The following table summarizes specifications across the Ascend generations:

Performance vs. NVIDIA: Benchmark Data

Chip-Level Benchmarks

The Ascend 950PR is the performance leader in China’s domestic AI hardware market. It delivers 2.87× the compute throughput of the NVIDIA H20 — the highest-spec GPU China can legally import as of 2025 under current export controls. The 950PR is also the only Chinese AI processor to support FP4 precision inference natively.

The comparison shifts when set against NVIDIA’s unrestricted hardware. The H100 SXM5, available globally but not in China, operates at approximately 1,979 TFLOPS at FP8 — giving it a lead over the 950PR at the chip level. However, Chinese AI labs are not competing with unrestricted hardware; they are competing with what is actually available to them.

Precision and Software Compatibility

The Ascend 950 series introduces HiBL 1.0, Huawei’s proprietary high-bandwidth link interconnect — a functional alternative to NVIDIA’s NVLink for binding multiple chips into a coherent compute fabric. HiBL 1.0 is essential for multi-chip training runs where inter-chip bandwidth bottlenecks can cancel out raw compute gains.

For software portability, the Ascend 950 introduces SIMT (Single Instruction Multiple Threads) support. SIMT allows CUDA-written workloads to run on Ascend hardware with reduced porting effort — a significant barrier reduction for developers migrating from NVIDIA. Full compatibility is still evolving, but the SIMT layer handles a growing subset of common deep learning operators used in LLM training and inference.

Atlas SuperPoD and SuperCluster: System-Level Architecture

Individual chip specs matter less than system-level performance at frontier AI training scale. Huawei’s Atlas product line assembles Ascend chips into rack-scale and cluster-scale systems that compete directly with NVIDIA’s DGX SuperPOD.

Atlas 950 SuperPoD Specs

The Atlas 950 SuperPoD is Huawei’s primary rack-scale AI system. It houses 8,192 Ascend 950 chips across 128 compute racks plus 32 storage and networking racks, occupying roughly 1,000 m² of data-center floor space. At that configuration, it delivers aggregate AI compute that dwarfs anything NVIDIA currently ships as an integrated product.

Compared to NVIDIA’s NVL144 system — the largest integrated NVIDIA unit — the Atlas 950 SuperPoD is 56.8x larger in scale, provides 6.7x the aggregate compute, and 15x the total memory capacity at 1,152 TB. The Atlas 960 SuperPoD scales further, housing 15,488 chips across 176 compute racks plus 44 support racks in approximately 2,200 m².

The table below sets the two systems side by side:

Atlas 950 SuperCluster

Connecting multiple SuperPoDs yields the Atlas 950 SuperCluster: more than 520,000 Ascend chips delivering 524 EFLOPS of compute — 2.5x the scale of xAI’s Colossus supercomputer, which briefly held the title of the world’s largest AI training cluster. The Atlas 950 SuperCluster also operates at 1.3x the power efficiency of Colossus on a per-EFLOP basis.

The Atlas 960 SuperCluster, derived from the upcoming 960 chip generation, targets a million-chip configuration delivering 2 ZFLOPS at FP8 and 4 ZFLOPS at FP4 — numbers that would represent a qualitative step change in available AI compute capacity.

“Huawei’s Ascend roadmap demonstrates that large-scale frontier AI training is achievable independent of U.S. technology. The Atlas 950 SuperCluster’s compute capacity already exceeds that of the leading U.S. AI training clusters available to commercial players.”

Eric Xu, Huawei Rotating Chairman, Ascend Roadmap Announcement

Manufacturing: SMIC, DUV, and the Yield Challenge

How Huawei Makes Chips Without TSMC

HiSilicon designs the Ascend chips; SMIC (Semiconductor Manufacturing International Corporation) manufactures them using 7nm-class DUV (Deep Ultraviolet) lithography — the most advanced node achievable without ASML’s EUV machines, which are blocked from export to China. EUV enables yields above 80% at leading nodes; DUV at 7nm delivers approximately 30%, meaning 70% of fabricated wafers produce non-functional dies.

This yield constraint makes each working Ascend die more expensive than comparable TSMC-manufactured chips — but Huawei addresses this through volume and vertical integration. By controlling HiSilicon (design), SMIC (manufacturing), and Atlas (system integration), Huawei absorbs yield losses across the supply chain without depending on external suppliers subject to export controls.

How a Huawei Ascend chip reaches a data center:

1. HiSilicon completes chip design and submits to SMIC for fabrication
2. SMIC runs 7nm DUV wafers — approximately 30% yield on functional dies
3. Functional dies are packaged with HiZQ 2.0 HBM and UnifiedBus 2.0 interconnect
4. Packaged chips are tested and binned by performance tier
5. Qualified chips are installed into Atlas 800T A2 or Atlas 900 servers
6. Servers are racked into Atlas SuperPoD configurations
7. SuperPoDs interconnect via HiBL 1.0 fabric into SuperCluster deployments

UnifiedBus 2.0 and HiZQ 2.0

The Ascend 950DT introduces HiZQ 2.0 high-bandwidth memory — Huawei’s proprietary HBM alternative. Standard HBM from SK Hynix and Micron is subject to US export restrictions for Chinese buyers; HiZQ 2.0 is domestically produced, removing that dependency entirely. UnifiedBus 2.0 provides the high-speed chip-to-chip interconnect that ties Ascend chips into a coherent fabric within Atlas systems, delivering 2 TB/s chip-to-chip bandwidth on the 950DT.

The combination of HiZQ 2.0 and UnifiedBus 2.0 means the Ascend 950 generation is, for the first time, a fully domestically sourced AI accelerator from silicon to memory to interconnect — a milestone that matters as much strategically as it does technically.

Z.ai and GLM Models on Ascend: Real-World Deployment

Zhipu AI’s Commitment to Ascend Hardware

Zhipu AI — the team behind Z.ai — built its entire training and inference stack on Huawei Ascend after US export restrictions made NVIDIA hardware unavailable. GLM-5, a 744-billion-parameter frontier model, was trained on a cluster of 100,000 Ascend 910B chips. The follow-on GLM-Image generation model was trained entirely on Atlas 800T A2 servers through Huawei’s MindSpore framework, achieving a CVTG-2K benchmark score of 0.9116 — a competitive result by international standards for image generation quality.

Zhipu AI’s deployment is the most extensively documented case of frontier-scale training on Ascend hardware, and it establishes a benchmark for what the chipset can achieve in production rather than in controlled benchmarks.

GLM-5 and AutoGLM: The Z.ai Model Family

The GLM-5 model family powers Z.ai’s reasoning capabilities at production scale, while AutoGLM handles agentic tasks and automated workflows — both running inference on Ascend-based clusters. The Z.ai platform’s independence from NVIDIA hardware is now a structural feature of its architecture, not a temporary workaround. This means Z.ai can scale compute capacity by purchasing Ascend chips domestically, without exposure to export control risk.

MindSpore: The Ascend Software Stack

MindSpore is Huawei’s open-source AI framework, analogous to PyTorch or TensorFlow but optimized specifically for Ascend hardware. It provides operator libraries, auto-differentiation, and distributed training primitives that allow researchers to write code targeting Ascend chips without manual low-level optimization. The framework handles the mapping between standard deep learning operations and Ascend’s native instruction set. The full MindSpore documentation is maintained by Huawei and covers Ascend 910 through 950 series integration.

Huawei has invested heavily in CUDA compatibility layers within MindSpore and SIMT support on Ascend 950 to ease migration from NVIDIA ecosystems. Developers porting PyTorch-based training code report that common transformer architectures run with relatively few changes — a deliberate design choice to reduce switching costs for labs that previously built on CUDA.

MindSpore’s core capabilities relevant to Ascend deployments include:

• Automatic operator fusion and memory layout optimization for Ascend tensor cores
• Distributed training across thousands of Ascend chips with gradient checkpointing
• CUDA-to-Ascend translation layer via SIMT, covering common transformer operators
• Integration with Atlas 800T A2 servers for single-node and multi-node inference
• Model Zoo with pre-trained GLM, BERT, and vision models adapted for Ascend

US Export Restrictions and China’s AI Chip Independence

The January 2025 Turning Point

The US Commerce Department’s January 2025 export control update blocked virtually all high-performance AI chips — including the NVIDIA H20 — from being sold to Chinese entities. This extended earlier controls that had already restricted A100 and H100 exports. The result was a near-complete severance of China’s AI labs from the global supply of frontier-class AI hardware.

Huawei’s response was swift: the Ascend roadmap accelerated, production volumes expanded, and Chinese AI labs formalized their Ascend-first strategies. By mid-2026, NVIDIA’s share of the Chinese data-center AI chip market had effectively reached zero. The export controls intended to slow China’s AI capabilities appear instead to have accelerated the development of an independent domestic AI hardware ecosystem.

Revenue and Market Position

Huawei reported approximately $7.5 billion in AI chip revenue in 2025. The company projected $12 billion for 2026, making Huawei the dominant supplier of data-center AI compute in China by a substantial margin. Cambricon and Moore Threads serve secondary roles in the domestic AI hardware ecosystem — particularly for inference and edge deployment — but Ascend chips command the frontier training workloads where performance per watt and interconnect bandwidth matter most.

The following revenue trajectory reflects how rapidly the market shifted:

• 2023: Huawei begins shipping Ascend 910B at scale to Chinese hyperscalers
• 2024: Ascend orders surge as NVIDIA H800 export licenses are revoked; revenue approximately $4 billion
• 2025: H20 ban confirmed; Huawei AI chip revenue reaches $7.5 billion
• 2026 (projected): $12 billion, driven by Ascend 950 production ramp

Implications for Global AI

The Ascend ecosystem demonstrates that large-scale frontier AI training is achievable without TSMC EUV or NVIDIA GPUs. With Atlas 950 SuperClusters already outpacing xAI’s Colossus in raw scale, and Atlas 960 clusters targeting ZFLOP-scale compute, China’s AI infrastructure trajectory is no longer dependent on US-controlled technology. The ChatGLM technical research published via the ChatGLM technical report documents how Zhipu AI adapted training methodologies for Ascend architecture, providing a public reference for the software adaptations required at scale.

The implication for the global AI industry is significant: the assumption that frontier AI requires NVIDIA hardware and TSMC fabrication no longer holds. Two parallel AI compute ecosystems now exist, with Ascend and NVIDIA developing largely independently of one another.

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